Google Inc., Software Engineering Google Brain, June 2020 - present
- Compilation of deep learning models to TPUs.
Google Inc., Software Engineering Intern, September 2018 - December 2018
Worked with “Google kernel performance” team to augment the perf tools with Topdown Analysis capability. Developed from scratch an “Intel Topdown” converter that we will be released to the open-source community. This will make the Intel Topdown bottleneck analysis methodology more visible and practical.
Developed proof-of-concept prototypes to achieve data profile symbolization. Given a set of hot load/store instructions (generated by sampling the application using tools like perf), the problem is to find the type of the data address associated with those instructions. Such information is useful in optimizing memory allocation strategies or cache utilization. Deployed LLVM based tools implementing approaches based on: (1) Allocation Based Profiling and (2) Dwarf debug Info.
Google Inc., Software Engineering Intern, May 2017 - August 2017
Worked with “Google continuous profiling and efficiency” team to augment the profiling tools with analysis capable of guiding the service owners to pinpoint unexpected performance changes (called havocs in this work) in CPU time.
- Investigated the effectiveness of existing strategies in literature and open source.
- Developed a statistical Go tool which determines potential havocs amid noisy data with low false positive rate.
Apple Inc., Compiler Engineer, Compiler Research Intern, April 2016 - August 2016
Worked as a member of Swift Performance Team on an exploratory project which requires sound knowledge in compiler backend. Achieved functional completeness with real work loads.
Intel Technology Pvt. Ltd., Component Design Engineer, August 2011 - June 2013
- Worked as Design Automation Engineer for Formal Equivalence Verification (FEV) of hardware designs.
- Contributed to and supported Broadwell (BDX) and Skylake (SKL) FEV requirements. Played key role in FEV audit checks for BDX.
- Owner of tools and infrastructures for driving FEV central runs for BDX. Worked closely with teams of various design styles in understanding the requirements for customization and also provided the much needed support for successfully deploying those tools.
- Build flows and methodologies to provide solutions on how to formally verify leading next generation CPU designs. Interacted closely with global FEV teams to understand the requirements and contributed to the success of various sprints with timely and quality delivery on assignments.
Interra Systems Pvt. Ltd., Senior Member Of Technical Staff, August 2006 - July 2009
- Developer of Interra’s premiere front-end analyzer products - Cheetah (SystemVerilog) and MVV(Mixed Verilog and provided support for several new constructs of System Verilog IEEE-1800-2005, fixed tool bugs, created applications and contributed in performance Improvement.
- Involved in a critical service project for Atrenta Pvt. Ltd. for the development of System Verilog features in Spyglass DFT.