Abstract: Clang based AST reformatting tool used for injecting instrumentation code in C/C++ programs. The goal is collecting profiles (run-times and execution frequencies) on C/C++ programs.
Abstract: To read type information from debug info section of executable using LLVM based APIs.
Abstract: Finding bugs in LLVM’s pointer analysis using a mix of static analysis and symbolic execution (using KLEE).
Abstract: PRE is a compiler optimization that eliminates expressions that are redundant on some but not necessarily all paths through a program. In this project, we implemented a PRE optimization pass in LLVM and measured results on a variety of applications.
Abstract: To Extend the Generic Data Flow Analyzer GDFA (of gcc) to the data flow frameworks where data flow information can be represented using bit vectors but the frameworks are not bit vector frameworks because they are non-separable e.g., faint variable analysis, possible undefined variable analysis, strongly live variable analysis.
Abstract: Designed a dynamically typed language and an interpreter for it and achieved a slowdown of 2X w.r.t the execution time of statically compiled C language. This is obtained by providing built-in compiled functions for simple graph computation which in turn help to build complex ones.
Mitigating Impact of Heterogeneity Across Power-constrained Nodes on Parallel Applications through Load Balancing
Abstract: Different processors across the nodes have different execution times for the same work-loads. This performance imbalance is seen only when the CPU power is capped to low values. This performance imbalance causes increased execution times of the parallel applications. We did a detailed study and proposed a power aware load balancer (using Charm++ ) which minimized the performance imbalance at the lower power caps by tackling this heterogeneity.
Abstract: To design a customized processor (using parallel processing concepts) for the application of document retrieval system. We developed a superscalar processor (with an issue rate of 2) using verilog hdl, and an assembler for that processor using flex and bison.
Abstract: We plan to leverage the state space search model for implementing graph coloring in parallel in Charm++. Some of the challenges for efficient exploration of space by chares include intelligent pruning of the state space, load balancing, grain-size control and low-overhead communication between chares. We evaluated multiple options for each of these, and come up with design decisions which would work for a large category of real-life graph applications.
Abstract: To disambiguate heap allocated data-structures by estimating the shape (Tree, Dag or Cyclic Graph ) of the data structure accessible from each heap directed pointer. This will help in automatic parallelization of sequential code having heap intensive data structures. The work mainly focuses on devising a novel shape analysis technique.